UPD78F9234MC-5A4-A Datasheet, PDF (415/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX E REVISION HISTORY
(3/6)
Edition
Description
Applied to:
3rd edition Deletion of description on (T) product, (S) product, (R) product, (T2) product
Throughout
Modification of 1.4 78K0S/Kx1+ Product Lineup
CHAPTER 1 OVERVIEW
Addition of Caution 2 to 3.2.1 (3) Stack pointer (SP)
CHAPTER 3 CPU
ARCHITECTURE
Modification of Figure 4-7 Block Diagram of P34
Addition of Caution to Figure 4-17 Format of Port Mode Control Register 2
CHAPTER 4 PORT
FUNCTIONS
Modification of Caution 2 in 6.2 (1) 16-bit timer counter 00 (TM00)
Addition of 6.5 (23) External clock limitation
CHAPTER 6 16-BIT
TIMER/EVENT COUNTER
00
Addition of Caution to Figure 10-8 Format of Port Mode Control Register 2
(PMC2)
CHAPTER 10 A/D
CONVERTER
Addition of 10.6 (10) Operating current at conversion waiting mode
Addition of Caution to 11.2 (1) Receive buffer register 6 (RXB6)
Addition of Caution 1 to and modification of Caution 3 in 11.2 (3) Transmit buffer
register 6 (TXB6)
CHAPTER 11 SERIAL
INTERFACE UART6
Correction of Note 3 in Figure 11-5 Format of Asynchronous Serial Interface
Operation Mode Register 6 (ASIM6) (1/2)
Addition of Notes 1 and 2 to and modification of Cautions 1, 2 and 3 in Figure 11-5
Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6)
(2/2)
Modification of Caution in 11.3 (6) Asynchronous serial interface control register
6 (ASICL6)
Modification of Caution 1 in Figure 11-10 Format of Asynchronous Serial
Interface Control Register 6 (ASICL6)
Modification of Caution in 11.4.2 (1) Registers used
Partial modification of description in 11.4.2 (2) (c) Normal transmission
Partial modification of description in and addition of Caution 1 to 11.4.2 (2) (d)
Continuous transmission
Addition of Caution 2 to 17.3 (2) Low-voltage detection level select register (LVIS) CHAPTER 17 LOW-
VOLTAGE DETECTOR
Addition of 18.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin CHAPTER 18 OPTION
(P34)
BYTE
Addition of description to 19.6.1 X1 and X2 pins
Addition of Remark 1 to 19.8 Flash Memory Programming by Self Writing
CHAPTER 19 FLASH
MEMORY
Modification of description of internal verify 1 in and addition of description and
Remark of internal verify 2 to Table 19-11 Self Programming Controlling
Commands
Partial modification of and addition to 19.8.2 Cautions on self programming
function
Addition of Cautions 2, 3 and 5 to and modification of Caution 4 in Figure 19-12
Format of Flash Programming Mode Control Register (FLPMC)
Modification of Caution in and addition of description on FPRERR to 19.8.3 (2) Flash
protect command register (PFCMD)
Addition of Caution to 19.8.3 (3) Flash status register (PFS)
User’s Manual U17446EJ5V0UD
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