UPD78F9234MC-5A4-A Datasheet, PDF (206/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 11 SERIAL INTERFACE UART6
(c) Normal transmission
When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1, and
then bit 6 (TXE6) of ASIM6 is set to 1 after one clock of the base clock (fXCLK6) has elapsed, transmission
enable status is entered. Transmission can be started by writing transmit data to transmit buffer register 6
(TXB6). The start bit, parity bit, and stop bit are automatically appended to the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and
stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated.
Transmission is stopped until the data to be transmitted next is written to TXB6.
Figure 11-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
Figure 11-15. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
TXD6 (output)
Start D0
D1
D2
D6 D7 Parity Stop
INTST6
2. Stop bit length: 2
TXD6 (output)
Start D0
D1
D2
D6
D7 Parity
Stop
INTST6
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User’s Manual U17446EJ5V0UD