 English |
|
|
|
|
|
|
|
| UPD78F9234MC-5A4-A Datasheet, PDF (340/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
| |||
| ◁ |
CHAPTER 21 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
SUBC
AND
OR
XOR
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
Bytes Clocks
Operation
2
4 A, CY â A â byte â CY
3
6 (saddr), CY â (saddr) â byte â CY
2
4 A, CY â A â r â CY
2
4 A, CY â A â (saddr) â CY
3
8 A, CY â A â (addr16) â CY
1
6 A, CY â A â (HL) â CY
2
6 A, CY â A â (HL + byte) â CY
2
4 A â A ⧠byte
3
6 (saddr) â (saddr) ⧠byte
2
4 AâAâ§r
2
4 A â A ⧠(saddr)
3
8 A â A ⧠(addr16)
1
6 A â A ⧠(HL)
2
6 A â A ⧠(HL + byte)
2
4 A â A ⨠byte
3
6 (saddr) â (saddr) ⨠byte
2
4 AâAâ¨r
2
4 A â A ⨠(saddr)
3
8 A â A ⨠(addr16)
1
6 A â A ⨠(HL)
2
6 A â A ⨠(HL + byte)
2
4 A â A ⨠byte
3
6 (saddr) â (saddr) ⨠byte
2
4 AâAâ¨r
2
4 A â A ⨠(saddr)
3
8 A â A ⨠(addr16)
1
6 A â A ⨠(HL)
2
6 A â A ⨠(HL + byte)
Flag
Z AC CY
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Ã
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
338
Userâs Manual U17446EJ5V0UD
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese