UPD78F9234MC-5A4-A Datasheet, PDF (118/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-30. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 000 (CR000)
fXP
fXP/2²
fXP/2⁸
TI000/INTP0/P30
Noise
eliminator
fXP
16-bit timer counter 00
(TM00)
Clear
circuit
16-bit timer capture/compare
register 010 (CR010)
Figure 6-31. PPG Output Operation Timing
t
Count clock
TM00 count value _N 0000H 0001H
Clear
CR000 capture value
CR010 capture value
TO00
M−1 M
N
M
N − 1 N 0000H 0001H
Clear
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
Remark 0000H < M < N ≤ FFFFH
TO00/TI010/
INTP2/P31
116
User’s Manual U17446EJ5V0UD