UPD78F9234MC-5A4-A Datasheet, PDF (363/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)
(A2) grade product TA = −40 to +125°C
DC Characteristics (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V) (2/2)
Parameter Symbol
Supply
current^{Note 2}
I ^{Note 3}
DD1
IDD2
I ^{Note 3}
DD3
IDD4
IDD5
Conditions
MIN. TYP. MAX. Unit
Crystal/ceramic
fX = 8 MHz
oscillation, external VDD = 5.0 V ±10%^{Note 4}
clock input
oscillation operating ^{fX = 6 MHz}
mode^{Note 6}
VDD = 5.0 V ±10%^{Note 4}
When A/D converter is stopped
When A/D converter is operating^{Note 8}
When A/D converter is stopped
When A/D converter is operating^{Note 8}
fX = 5 MHz
When A/D converter is stopped
VDD = 3.0 V ±10%^{Note 5} _{When A/D converter is operating}Note 8
5.8 12.8 mA
7.3 15.8
5.5 12.2 mA
15.2
3.0 6.6 mA
4.5 9.6
Crystal/ceramic
oscillation, external
clock input HALT
mode^{Note 6}
fX = 8 MHz
VDD = 5.0 V ±10%^{Note 4}
fX = 6 MHz
VDD = 5.0 V ±10%^{Note 4}
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
1.5 4.6 mA
7.6
1.3 4.2 mA
7.2
fX = 5 MHz
When peripheral functions are stopped
VDD = 3.0 V ±10%^{Note 5} _{When peripheral functions are operating}
0.48 1.6 mA
2.7
High-speed internal
oscillation operating
mode^{Note 7}
fX = 8 MHz
When A/D converter is stopped
VDD = 5.0 V ±10%^{Note 4} _{When A/D converter is operating}Note 8
5.0 12.2 mA
6.5 15.2
High-speed internal
oscillation HALT
mode^{Note 7}
fX = 8 MHz
When peripheral functions are stopped
VDD = 5.0 V ±10%^{Note 4} _{When peripheral functions are operating}
1.4 4.4 mA
7.1
STOP mode
VDD = 5.0 V ±10%
When low-speed internal
oscillation is stopped
3.5 1200 μA
When low-speed internal
oscillation is operating
17.5 1300
VDD = 3.0 V ±10%
When low-speed internal
oscillation is stopped
3.5 600 μA
When low-speed internal
oscillation is operating
11.0 700
Notes 1.
2.
3.
4.
5.
6.
7.
8.
Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.26 V (MAX.).
Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
Peripheral operation current is included.
When the processor clock control register (PCC) is set to 00H.
When the processor clock control register (PCC) is set to 02H.
When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using
the option byte.
When the high-speed internal oscillation clock is selected as the system clock source using the option
byte.
The current that flows through the AVREF pin is included.
User’s Manual U17446EJ5V0UD
361