UPD78F9234MC-5A4-A Datasheet, PDF (396/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(5/20)
Page
16-bit
timer/event
counter 00
PRM00:
Prescaler mode
register 00
Interval timer
External event
counter
Pulse width
measurement
Square-wave
output
PPG output
One-shot pulse
output by
software
The sampling clock used to eliminate noise differs when a TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is fXP, and in the latter case the count clock is selected
by prescaler mode register 00 (PRM00). The capture operation is not
performed until the valid edge is sampled and the valid level is detected twice,
thus eliminating noise with a short pulse width.
pp.
98, 127
When using P31 as the input pin (TI010) of the valid edge, it cannot be used pp.
as a timer output pin (TO00). When using P31 as the timer output pin (TO00), _{98, 127}
it cannot be used as the input pin (TI010) of the valid edge.
Changing the CR000 setting during TM00 operation may cause a malfunction. p.99
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
When reading the external event counter count value, TM00 should be read. pp.
103, 127
To use two capture registers, set the TI000 and TI010 pins.
pp.
104, 125
The measurable pulse width in this operation example is up to 1 cycle of the
timer counter.
pp.
105, 107,
108, 110
Changing the CR000 setting during TM00 operation may cause a malfunction. p.112
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
Changing the CRC0n0 setting during TM00 operation may cause a
malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit
Timer/Event Counter 00 (17) Changing compare register during timer
operation.
p.114
Values in the following range should be set in CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
pp.
115, 127
The cycle of the pulse generated through PPG output (CR000 setting value + pp.
1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).
115, 127
Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. pp.
To output the one-shot pulse again, wait until the current one-shot pulse
output is completed.
117, 123
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-
function port pin.
Because the external trigger is valid even in this case, the timer is cleared and
started even at the level of the TI000 pin or its alternate-function port pin,
resulting in the output of a pulse at an undesired timing.
pp.
117, 123
Do not set 0000H to the CR000 and CR010 registers.
pp.
118, 123
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC003 and TMC002 bits.
pp.
119, 122
394
User’s Manual U17446EJ5V0UD