UPD78F9234MC-5A4-A Datasheet, PDF (395/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(4/20)
Page
16-bit
timer/event
counter 00
TMC00: 16-bit The capture operation is performed at the fall of the count clock. An interrupt
timer mode control request input (INTTM0n0), however, occurs at the rise of the next count clock.
register 00
pp.
94, 125
CRC00: Capture
/compare control
register 00
The timer operation must be stopped before setting CRC00.
pp.
95, 123
When the clear & start mode entered on a match between TM00 and CR000 is pp.
selected by 16-bit timer mode control register 00 (TMC00), CR000 should not _{95, 122}
be specified as a capture register.
To ensure the reliability of the capture operation, the capture trigger requires a pp.
pulse longer than two cycles of the count clock selected by prescaler mode
register 00 (PRM00) (refer to Figure 6-17).
95, 125
TOC00: 16-bit
timer output
control register
00
The timer operation must be stopped before setting other than OSPT00.
If LVS00 and LVR00 are read, 0 is read.
pp.
96, 123
pp.
96, 123
OSPT00 is automatically cleared after data is set, so 0 is read.
pp.
96, 123
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
pp.
96, 123
A write interval of two cycles or more of the count clock selected by prescaler pp.
mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. _{96, 123}
When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the p.96
8-bit memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00
can be set with the 1-bit memory manipulation instruction.
PRM00:
Prescaler mode
register 00
Always set data to PRM00 after stopping the timer operation.
pp.
98, 123
If the valid edge of the TI000 pin is to be set as the count clock, do not set the _pp.
clear/start mode and the capture trigger at the valid edge of the TI000 pin.
98, 125
In the following cases, note with caution that the valid edge of the TI0n0 pin is
detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin,
the operation of the 16-bit timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the
valid edge of the TI0n0 pin, a rising edge is detected immediately after
the TM00 operation is enabled.
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00
operation is then enabled after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the
valid edge of the TI0n0 pin, a falling edge is detected immediately after
the TM00 operation is enabled.
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00
operation is then enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the
valid edge of the TI0n0 pin, a rising edge is detected immediately after
the TM00 operation is enabled.
pp.
98, 127
User’s Manual U17446EJ5V0UD
393