UPD78F9234MC-5A4-A Datasheet, PDF (409/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(18/20)
Page
Flash
memory
Self
programming
function
Since the security function set via on-board/off-board programming is disabled p.285
in self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase
processing during self programming, set the protect byte.
Be sure to clear bits 5 to 7 of flash address pointer H (FLAPH) and flash
address pointer H compare register (FLAPHC) to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
p.285
Clear the value of the FLCMD register to 00H immediately before setting to
self programming mode and normal mode.
p.285
FLPMC: Flash
programming
mode control
register
Cautions in the case of setting the self programming mode, refer to 19.8.2
Cautions on self programming function.
Set the CPU clock beforehand so that it is 1 MHz or higher during self
programming.
p.286
p.286
Execute self programming after executing the NOP and HALT instructions
immediately after executing a specific sequence to set self programming
mode. At this time, the HALT instruction is automatically released after 10 μs
(MAX.) + 2 CPU clocks (fCPU).
p.286
If the clock of the oscillator or an external clock is selected as the system
clock, execute the NOP and HALT instructions immediately after executing a
specific sequence to set self programming mode, wait for 8 μs after releasing
the HALT status, and then execute self programming.
p.286
Clear the value of the FLCMD register to 00H immediately before setting to
self programming mode and normal mode.
p.286
PFCMD: Flash
protect command
register
Interrupt servicing cannot be executed in self programming mode. Disable
interrupt servicing (by executing the DI instruction while MK0 and MK1 = FFH)
between the points before executing the specific sequence that sets self
programming mode and after executing the specific sequence that changes
the mode to the normal mode.
p.287
PFS: Flash
status register
Check FPRERR using a 1-bit memory manipulation instruction.
p.287
FLAPH and
FLAPL: Flash
address pointers
H and L
Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the
self programming command. If the self programming command is executed
with these bits set to 1, the device may malfunction.
p.290
FLAPHC and
FLAPLC: Flash
address pointer
H compare
register and flash
address pointer L
compare register
Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the
self programming command. If the self programming command is executed
with these bits set to 1, the device may malfunction.
Set the number of the block subject to a block erase, verify, or blank check
(same value as FLAPH) to FLAPHC.
Clear FLAPLC to 00H when a block erase is performed, and FFH when a
blank check is performed.
p.290
p.290
p.290
User’s Manual U17446EJ5V0UD
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