UPD78F9234MC-5A4-A Datasheet, PDF (259/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 16 POWER-ON-CLEAR CIRCUIT
16.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 16-1.
Figure 16-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
16.3 Operation of Power-on-Clear Circuit
In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V (TYP.)) are compared,
and an internal reset signal is generated when VDD < VPOC, and an internal reset is released when VDD ≥ VPOC.
Figure 16-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Supply voltage (VDD)
POC detection voltage
(VPOC = 2.1 V (TYP.))
Internal reset signal
Time
User’s Manual U17446EJ5V0UD
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