UPD78F9234MC-5A4-A Datasheet, PDF (234/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 13 INTERRUPT FUNCTIONS
(4) External interrupt mode register 1 (INTM1)
INTM1 is used to specify the valid edge for INTP3.
INTM1 is set with an 8-bit memory manipulation instruction.
Reset signal generation clears INTM1 to 00H.
Figure 13-5. Format of External Interrupt Mode Register 1 (INTM1)
Address: FFEDH After reset: 00H R/W
Symbol 7
6
5
4
3
2
1
0
INTM1
0
0
0
0
0
0
ES31 ES30
ES31 ES30
INTP3 valid edge selection
0
0 Falling edge
0
1 Rising edge
1
0 Setting prohibited
1
1 Both rising and falling edges
Cautions 1. Be sure to clear bits 2 to 7 to 0.
2. Before setting INTM1, set PMK3 to 1 to disable interrupts.
To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.
(5) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
Generation of reset signal sets PSW to 02H.
Figure 13-6. Program Status Word (PSW) Configuration
Symbol 7
6
5
4
3
2
1
0
PSW IE Z
0 AC 0
0
1 CY
After reset
02H
IE
0 Disabled
1 Enabled
Used in the execution of ordinary instructions
Whether to enable/disable interrupt acknowledgment
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User’s Manual U17446EJ5V0UD