UPD78F9234MC-5A4-A Datasheet, PDF (51/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier
−
[DE], [HL]
Description
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code 0 0 1 0 1 0 1 1
[Illustration]
15
DE
D
The contents of addressed
memory are transferred
7
A
87
7
0
0
E
Memory address specified
0
by register pair DE
User’s Manual U17446EJ5V0UD
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