UPD78F9234MC-5A4-A Datasheet, PDF (86/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATORS
Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation
Power
application
VDD > 2.1 V (TYP.)
Reset by
power-on-clear
Crystal/ceramic
oscillation selected
by option byte
Reset signal
Wait for clock
oscillation stabilization
Interrupt
HALT
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
HALT
instruction _STOP
instruction
Interrupt
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
(3) External clock input circuit
If external clock input is selected by the option byte, the following is possible.
• High-speed operation
The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))
because an oscillation frequency of 2 to 10 MHz can be selected and an external clock with a small frequency
deviation can be supplied.
• Improvement of expandability
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For
details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
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User’s Manual U17446EJ5V0UD