UPD78F9234MC-5A4-A Datasheet, PDF (397/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(6/20)
Page
16-bit
timer/event
counter 00
One-shot pulse
output with
external trigger
Do not input the external trigger again while the one-shot pulse is being
output. To output the one-shot pulse again, wait until the current one-shot
pulse output is completed.
pp.
119, 124
Do not set 0000H to the CR000 and CR010 registers.
pp.
120, 124
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC003 and TMC002 bits.
pp.
121, 122
Timer start errors
An error of up to one clock may occur in the time required for a match signal to p.122
be generated after timer start. This is because 16-bit timer counter 00 (TM00)
is started asynchronously to the count clock.
One-shot pulse
output
One-shot pulse output normally operates only in the free-running mode or in
the clear & start mode at the valid edge of the TI000 pin. Because an overflow
does not occur in the clear & start mode on a match between TM00 and
CR000, one-shot pulse output is not possible.
p.123
Capture
operation
If both the rising and falling edges are selected as the valid edges of the TI000 p.125
pin, capture is not performed.
When the CRC001 bit value is 1, the TM00 count value is not captured in the
CR000 register when a valid edge of the TI010 pin is detected, but the input
from the TI010 pin can be used as an external interrupt source because
INTTM000 is generated at that timing.
p.125
Changing
compare register
during timer
operation
With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a
compare register, when changing CR0n0 around the timing of a match
between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare
register 0n0 (CR0n0) during timer counting, the change timing may conflict
with the timing of the match, so the operation is not guaranteed in such cases.
To change CR0n0 during timer counting, follow the procedure below using an
INTTM000 interrupt.
p.126
If CR010 is changed during timer counting without performing processing <1>
above, the value in CR010 may be rewritten twice or more, causing an
inversion of the output level of the TO00 pin at each rewrite.
p.126
External event
counter
The timing of the count start is after two valid edge detections.
p.127
External clock
limitation
When using an input pulse of the TI000 pin as a count clock (external trigger),
be sure to input the pulse width which satisfies the AC characteristics. For the
AC characteristics, refer to CHAPTER 22 and CHAPTER 23 ELECTRICAL
SPECIFICATIONS.
p.128
When an external waveform is input to 16-bit timer/event counter 00, it is
sampled by the noise limiter circuit and thus an error occurs on the timing to
become valid inside the device.
p.128
8-bit timer
80
CR80: 8-bit
compare register
80
When changing the value of CR80, be sure to stop the timer operation. If the
value of CR80 is changed with the timer operation enabled, a match interrupt
request signal is generated immediately and the timer may be cleared.
p.131
TMC80: 8-bit
timer mode
control register
80
Be sure to set TMC80 after stopping the timer operation.
Be sure to clear bits 0 and 6 to 0.
p.132
p.132
User’s Manual U17446EJ5V0UD
395