UPD78F9234MC-5A4-A Datasheet, PDF (78/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATORS
The fastest instruction of the 78K0S/KB1+ is executed in two CPU clocks. Therefore, the relationship between the
CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU) ^Note
fX
fX/2
fX/2²
fX/2³
fX/2⁴
Minimum Instruction Execution Time: 2/fCPU
High-speed internal oscillation clock
(at 8.0 MHz (TYP.))
Crystal/ceramic oscillation clock
or external clock input (at 10.0 MHz)
0.25 μs
0.2 μs
0.5 μs
0.4 μs
1.0 μs
0.8 μs
2.0 μs
1.6 μs
4.0 μs
3.2 μs
Note The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock, or external clock
input) is selected by the option byte.
(2) Low-speed internal oscillation mode register (LSRCM)
This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)).
This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped
by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by
software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition,
the source clock of WDT is fixed to the low-speed internal oscillator. For details, refer to CHAPTER 9
WATCHDOG TIMER.
LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.
Generation of reset signal sets LSRCM to 00H.
Figure 5-4. Format of Low-Speed Internal Oscillation Mode Register (LSRCM)
Address: FF58H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
LSRCM
0
0
0
0
0
0
0
LSRSTOP
LSRSTOP
Oscillation/stop of low-speed internal oscillator
0
Low-speed internal oscillates
1
Low-speed internal oscillator stops
76
User’s Manual U17446EJ5V0UD