UPD78F9234MC-5A4-A Datasheet, PDF (84/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATORS
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation
clock operates as the system clock.
Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation
Power
application
VDD > 2.1 V (TYP.)
Reset by
power-on-clear
Reset signal
High-speed internal
oscillator selected
by option byte
Start with PCC = 02H,
PPCC = 02H
Interrupt
HALT
Clock division ratio
variable during
CPU operation
HALT
instruction _STOP
instruction
Interrupt
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
(2) Crystal/ceramic oscillator
If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 to 10 MHz can be selected and
the accuracy of processing is improved because the frequency deviation is small, as compared with high-speed
internal oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
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User’s Manual U17446EJ5V0UD