UPD78F9234MC-5A4-A Datasheet, PDF (405/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(14/20)
Page
Interrupt
function
Standby
function
Vector table
address
No interrupt sources correspond to the vector table address 0014H.
p.226
IF0, IF1: Interrupt
request flag
registers 0, 1
MK0, MK1:
Interrupt mask
flag registers 0, 1
Because P30, P31, P41, and P43 have an alternate function as external
interrupt inputs, when the output level is changed by specifying the output
mode of the port function, an interrupt request flag is set. Therefore, the
interrupt mask flag should be set to 1 before using the output mode.
pp.
229, 230
INTM0: External
interrupt mode
register 0
Be sure to clear bits 0 and 1 to 0.
Before setting the INTM0 register, be sure to set the corresponding interrupt
mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register,
clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag
(××MK× = 0), which will enable interrupts.
p.231
p.231
INTM1: External
interrupt mode
register 1
Be sure to clear bits 2 to 7 to 0.
Before setting INTM1, set PMK3 to 1 to disable interrupts.
To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.
p.232
p.232
Interrupt request
pending
Interrupt requests will be held pending while the interrupt request flag registers p.235
0, 1 (IF0, IF1) or interrupt mask flag registers 0, 1 (MK0, MK1) are being
accessed.
Multiple interrupt Multiple interrupts can be acknowledged even for low-priority interrupts.
servicing
p.236
−
The LSRSTOP setting is valid only when “Can be stopped by software” is set p.238
for the low-speed internal oscillator by the option byte.
STOP mode
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware
that operates on the low-speed internal oscillation clock).
p.239
STOP mode,
HALT mode
The following sequence is recommended for operating current reduction of the
A/D converter when the standby function is used: First clear bit 7 (ADCS) and
bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D
conversion operation, and then execute the HALT or STOP instruction.
p.239
STOP mode
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 14-1).
p.239
OSTS:
Oscillation
stabilization time
select register
To set and then release the STOP mode, set the oscillation stabilization time
as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization
time set by OSTS
p.240
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
p.240
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER
18 OPTION BYTE.
p.240
User’s Manual U17446EJ5V0UD
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