UPD78F9234MC-5A4-A Datasheet, PDF (105/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-15. External Event Counter Configuration Diagram
Internal bus
fXP
Noise eliminator
16-bit timer capture/compare
register 000 (CR000)
Match
Clear
16-bit timer counter 00 (TM00)
INTTM000
OVF00^Note
Valid edge of TI000
Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH.
Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified)
(1) INTTM000 generation timing immediately after operation starts
Counting is started after a valid edge is detected twice.
TI000 pin input
TM00 count value
Timer operation starts
Count starts
123
0000H 0001H 0002H 0003H
N-2 N-1 N 0000H 0001H 0002H
CR000
N
INTTM000
(2) INTTM000 generation timing after INTTM000 has been generated twice
TI000 pin input
TM00 count value N 0000H 0001H 0002H 0003H 0004H
CR000
N
INTTM000
N-1 N 0000H 0001H 0002H 0003H
Caution When reading the external event counter count value, TM00 should be read.
User’s Manual U17446EJ5V0UD
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