UPD78F9234MC-5A4-A Datasheet, PDF (394/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(3/20)
Page
16-bit
timer/event
counter 00
CR000: 16-bit
timer capture/
compare register
000
If the register read period and the input of the capture trigger conflict when
pp.
CR000 is used as a capture register, the capture trigger input takes
91, 125
precedence and the read data is undefined. Also, if the count stop of the timer
and the input of the capture trigger conflict, the capture trigger is undefined.
Changing the CR000 setting during TM00 operation may cause a malfunction. p.92
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
CR010: 16-bit
timer capture/
compare register
010
In the free-running mode and in the clear & start mode using the valid edge of
the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is
generated when CR010 changes from 0000H to 0001H following overflow
(FFFFH).
pp.
92, 122
If the new value of CR010 is less than the value of 16-bit timer counter 0
(TM00), TM00 continues counting, overflows, and then starts counting from 0
again. If the new value of CR010 is less than the old value, therefore, the
timer must be reset to be restarted after the value of CR010 is changed.
pp.
92, 122
The value of CR010 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
pp.
92, 123
The capture operation may not be performed for CR010 set in compare mode pp.
even if a capture trigger is input.
92, 126
If the register read period and the input of the capture trigger conflict when
CR010 is used as a capture register, the capture trigger input takes
precedence and the read data is undefined. Also, if the timer count stop and
the input of the capture trigger conflict, the capture data is undefined.
pp.
93, 125
Changing the CR010 setting during TM00 operation may cause a malfunction. p.93
To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event
Counter 00 (17) Changing compare register during timer operation.
TMC00: 16-bit
timer mode
control register
00
16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and pp.
TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. _{93, 122}
Set TMC002 and TMC003 to 0, 0 to stop the operation.
The timer operation must be stopped before writing to bits other than the
OVF00 flag.
pp.
94, 123
If the timer is stopped, timer counts and timer interrupts do not occur, even if a pp.
signal is input to the TI000/TI010 pins.
94, 122
Except when the valid edge of the TI000 pin is selected as the count clock,
stop the timer operation before setting STOP mode or system clock stop
mode; otherwise the timer may malfunction when the system clock starts.
pp.
94, 127
Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register pp.
00 (PRM00) after stopping the timer operation.
94, 123
If the clear & start mode entered on a match between TM00 and CR000, clear p.94
& start mode at the valid edge of the TI000 pin, or free-running mode is
selected, when the set value of CR000 is FFFFH and the TM00 value changes
from FFFFH to 0000H, the OVF00 flag is set to 1.
Even if the OVF00 flag is cleared before the next count clock is counted
(before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the
OVF00 flag is re-set newly and clear is disabled.
pp.
94, 124
392
User’s Manual U17446EJ5V0UD