UPD78F9234MC-5A4-A Datasheet, PDF (407/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(16/20)
Page
Low-
voltage
detector
When used as
reset
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIM is set to 1, an
internal reset signal is not generated.
p.263
p.263
Cautions for low-
voltage detector
In a system where the supply voltage (VDD) fluctuates for a certain period in
the vicinity of the LVI detection voltage (VLVI), the operation is as follows
depending on how the low-voltage detector is used.
<1> When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (1) below.
<2> When used as interrupt
Interrupt requests may be frequently generated. Take action (2) below.
p.266
Option byte
Oscillation
stabilization time
on power
application or
after reset
release
The setting of this option is valid only when the crystal/ceramic oscillation clock p.270
is selected as the system clock source. No wait time elapses if the high-speed
internal oscillation clock or external clock input is selected as the system clock
source.
Control of
RESET pin
Because the option byte is referenced after reset release, if a low level is input
to the RESET pin before the option byte is referenced, then the reset state is
not released.
Also, when setting 0 to RMCE, connect the pull-up resistor.
p.270
Selection of
system clock
source
Because the X1 and X2 pins are also used as the P121 and P122 pins, the p.270
conditions under which the X1 and X2 pins can be used differ depending on
the selected system clock source.
(1) Crystal/ceramic oscillation clock is selected
The X1 and X2 pins cannot be used as I/O port pins because they are used
as clock input pins.
(2) External clock input is selected
Because the X1 pin is used as an external clock input pin, P121 cannot be
used as an I/O port pin.
(3) High-speed internal oscillation clock is selected
P121 and P122 can be used as I/O port pins.
Low-speed
internal oscillates
If it is selected that low-speed internal oscillator cannot be stopped, the count
clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation
clock.
p.271
If it is selected that low-speed internal oscillator can be stopped by software,
supply of the count clock to WDT is stopped in the HALT/STOP mode,
regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal
oscillation mode register (LSRCM). Similarly, clock supply is also stopped
when a clock other than the low-speed internal oscillation clock is selected as
a count clock to WDT.
While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock
can be supplied to the 8-bit timer H1 even in the STOP mode.
p.271
User’s Manual U17446EJ5V0UD
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