UPD78F9234MC-5A4-A Datasheet, PDF (103/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-12. Timing of Interval Timer Operation
t
Count clock
TM00 count value 0000H 0001H
N 0000H 0001H
N 0000H 0001H
N
Timer operation enabled
Clear
Clear
CR000
N
N
N
N
INTTM000
Interrupt request generated Interrupt request generated
Remark Interval time = (N + 1) × t
N = 0001H to FFFFH (settable range)
When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare
register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,
overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N)
before the change, it is necessary to restart the timer after changing CR000.
Figure 6-13. Timing After Change of Compare Register During Timer Count Operation (N → M: N > M)
Count clock
CR000
N
M
TM00 count value
X–1
X
FFFFH
0000H
0001H
0002H
Remark N > X > M
6.4.2 External event counter operation
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-14 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set any value to the CR000 register (0000H cannot be set).
<4> Set the TMC00 register to start the operation (see Figure 6-14 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 3 (PM3).
2. For how to enable the INTTM000 interrupt, see CHAPTER 13 INTERRUPT FUNCTIONS.
User’s Manual U17446EJ5V0UD
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