UPD78F9234MC-5A4-A Datasheet, PDF (406/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(15/20)
Page
Standby
function
Settings and
operating
statuses in HALT
mode
Because an interrupt request signal is used to clear the standby mode, if there p.241
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set.
Settings and
operating
statuses in STOP
mode
Because an interrupt request signal is used to clear the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set. Thus, in the STOP
mode, the normal operation mode is restored after the STOP instruction is
executed and then the operation is stopped for 34 μs (TYP.) (after an
additional wait time for stabilizing the oscillation set by the oscillation
stabilization time select register (OSTS) has elapsed when crystal/ceramic
oscillation is used).
p.244
Reset
function
−
For an external reset, input a low level for 2 μs or more to the RESET pin.
p.248
During reset signal generation, the system clock and low-speed internal
oscillation clock stop oscillating.
p.248
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KB1+
is reset if a low level is input to the RESET pin after reset is released by the
POC circuit, the LVI circuit and the watchdog timer and before the option byte
is referenced again. The reset status is retained until a high level is input to
the RESET pin.
p.248
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
p.249
Timing of reset
by overflow of
watchdog timer
The watchdog timer is also reset in the case of an internal reset of the
watchdog timer.
p.251
RESF: Reset
control flag
register
Do not read data by a 1-bit memory manipulation instruction.
p.255
Power-on- Functions of
clear circuit power-on-clear
circuit
If an internal reset signal is generated in the POC circuit, the reset control flag p.256
register (RESF) is cleared to 00H.
Use these products in the following voltage range because the detection
voltage (VPOC) of the POC circuit is the supply voltage range.
Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to
5.5 V
p.256
Cautions for
power-on-clear
circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in
the vicinity of the POC detection voltage (VPOC), the system may be
repeatedly reset and released from the reset status. In this case, the time
from release of reset to the start of the operation of the microcontroller can be
arbitrarily set by taking the following action.
p.258
Low-
voltage
detector
LVIM: Low-
voltage detect
register
To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
p.261
Be sure to set bits 2 to 6 to 0.
p.261
LVIS: Low-
voltage detection
level select
register
Bits 4 to 7 must be set to 0.
If values other than same values are written during LVI operation, the value
becomes undefined at the very moment it is written, and thus be sure to stop
LVI (bit 7 of LVIM register (LVION) = 0) before writing.
p.262
p.262
404
User’s Manual U17446EJ5V0UD