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UPD78F9234MC-5A4-A Datasheet, PDF (350/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)
Standard product, (A) grade product TA = −40 to +85°C
DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2)
Parameter Symbol
Conditions
MIN. TYP. MAX. Unit
Supply
I Note 3
DD1
currentNote 2
Crystal/ceramic
oscillation, external
clock input oscillation
operating modeNote 6
fX = 10 MHz
VDD = 5.0 V ±10%Note 4
fX = 6 MHz
VDD = 5.0 V ±10%Note 4
When A/D converter is stopped
When A/D converter is operatingNote 8
When A/D converter is stopped
When A/D converter is operatingNote 8
6.1 12.2 mA
7.6 15.2
5.5 11.0 mA
14.0
fX = 5 MHz
When A/D converter is stopped
VDD = 3.0 V ±10%Note 5 When A/D converter is operatingNote 8
3.0 6.0 mA
4.5 9.0
IDD2
Crystal/ceramic
fX = 10 MHz
When peripheral functions are stopped
oscillation, external
clock input HALT
modeNote 6
VDD = 5.0 V ±10%Note 4 When peripheral functions are operating
fX = 6 MHz
When peripheral functions are stopped
VDD = 5.0 V ±10%Note 4 When peripheral functions are operating
1.7 3.8 mA
6.7
1.3 3.0 mA
6.0
fX = 5 MHz
When peripheral functions are stopped
VDD = 3.0 V ±10%Note 5 When peripheral functions are operating
0.48 1 mA
2.1
I Note 3
DD3
High-speed internal
oscillation operating
modeNote 7
fX = 8 MHz
When A/D converter is stopped
VDD = 5.0 V ±10%Note 4 When A/D converter is operatingNote 8
5.0 10.0 mA
6.5 13.0
IDD4
High-speed internal fX = 8 MHz
When peripheral functions are stopped
oscillation HALT
modeNote 7
VDD = 5.0 V ±10%Note 4 When peripheral functions are operating
1.4 3.2 mA
5.9
IDD5
STOP mode
VDD = 5.0 V ±10%
When low-speed internal
oscillation is stopped
3.5 20.0 μA
When low-speed internal
oscillation is operating
17.5 32.0
VDD = 3.0 V ±10%
When low-speed internal
oscillation is stopped
3.5 15.5 μA
When low-speed internal
oscillation is operating
11.0 26.0
Notes 1.
2.
3.
4.
5.
6.
7.
8.
Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V ±0.1 V.
Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
Peripheral operation current is included.
When the processor clock control register (PCC) is set to 00H.
When the processor clock control register (PCC) is set to 02H.
When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using
the option byte.
When the high-speed internal oscillation clock is selected as the system clock source using the option
byte.
The current that flows through the AVREF pin is included.
348
User’s Manual U17446EJ5V0UD