UPD78F9234MC-5A4-A Datasheet, PDF (171/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 10 A/D CONVERTER
Notes
2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 3
and 4 below are satisfied.
Example When AVREF ≥ 2.7 V, fXP = 8 MHz
• The sampling time is 11.0 μs or more and the A/D conversion time is 14.0 μs or
more and 100 μs or less.
• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
3. Set the sampling time as follows.
• AVREF ≥ 4.5 V: 1.0 μs or more
• AVREF ≥ 4.0 V: 2.4 μs or more
• AVREF ≥ 2.85 V: 3.0 μs or more
• AVREF ≥ 2.7 V: 11.0 μs or more
4. Set the A/D conversion time as follows.
• AVREF ≥ 4.5 V: 3.0 μs or more and less than 100 μs
• AVREF ≥ 4.0 V: 4.8 μs or more and less than 100 μs
• AVREF ≥ 2.85 V: 6.0 μs or more and less than 100 μs
• AVREF ≥ 2.7 V: 14.0 μs or more and less than 100 μs
5. Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4.
6. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 μs from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 μs or more
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over
the first conversion result. If the ADCS is set to 1 without waiting for 1 μs or longer, ignore the
first conversion data.
ADCS
0
0
1
ADCE
0
1
×
Table 10-2. Settings of ADCS and ADCE
A/D Conversion Operation
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only comparator consumes power)
Conversion mode
Figure 10-4. Timing Chart When Comparator Is Used
ADCE
Comparator operating
Comparator
ADCS
Conversion
operation
Conversion
waiting
Conversion
operation
Note
Conversion stopped
Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 μs or
longer to stabilize the internal circuit.
Caution
1. The above sampling time and conversion time do not include the clock frequency error.
Select the sampling time and conversion time such that Notes 3 and 4 above are satisfied,
while taking the clock frequency error into consideration (an error margin maximum of ±5%
when using the high-speed internal oscillator).
User’s Manual U17446EJ5V0UD
169