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| UPD78F9234MC-5A4-A Datasheet, PDF (341/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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CHAPTER 21 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
CMP
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Bytes Clocks
Operation
2
4 A â byte
3
6 (saddr) â byte
2
4 Aâr
2
4 A â (saddr)
3
8 A â (addr16)
1
6 A â (HL)
2
6 A â (HL + byte)
3
6 AX, CY â AX + word
3
6 AX, CY â AX â word
3
6 AX â word
2
4 râr+1
2
4 (saddr) â (saddr) + 1
2
4 rârâ1
2
4 (saddr) â (saddr) â 1
1
4 rp â rp + 1
1
4 rp â rp â 1
1
2
(CY, A7 â A0, Amâ1 â Am) Ã 1
1
2
(CY, A0 â A7, Am+1 â Am) Ã 1
1
2
(CY â A0, A7 â CY, Amâ1 â Am) Ã 1
1
2
(CY â A7, A0 â CY, Am+1 â Am) Ã 1
3
6 (saddr.bit) â 1
3
6 sfr.bit â 1
2
4 A.bit â 1
3
6 PSW.bit â 1
2
10 (HL).bit â 1
3
6 (saddr.bit) â 0
3
6 sfr.bit â 0
2
4 A.bit â 0
3
6 PSW.bit â 0
2
10 (HL).bit â 0
1
2 CY â 1
1
2 CY â 0
1
2 CY â CY
Flag
Z AC CY
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃÃ
ÃÃ
ÃÃ
ÃÃ
ÃÃ
Ã
Ã
Ã
Ã
ÃÃÃ
ÃÃÃ
1
0
Ã
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
Userâs Manual U17446EJ5V0UD
339
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