UPD78F9234MC-5A4-A Datasheet, PDF (266/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 17 LOW-VOLTAGE DETECTOR
Figure 17-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
Supply voltage (VDD)
LVI detection voltage
(VLVI)
POC detection voltage
(VPOC)
<2>
LVIMK flag
(set by software) ^H
<1>
Note 1
LVION flag
(set by software)
LVIF flag
LVIMD flag
(set by software)
Not cleared
<3>
<4> 0.2 ms or longer
<5>
Note 2
<6>
Not cleared
LVIRF flag^{Note 3}
Not cleared
Not cleared
Clear
Clear
Clear
Time
LVI reset signal
POC reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 15
RESET FUNCTION.
Remark <1> to <6> in Figure 17-4 above correspond to <1> to <6> in the description of “when starting operation”
in 17.4 (1) When used as reset.
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User’s Manual U17446EJ5V0UD