UPD78F9234MC-5A4-A Datasheet, PDF (264/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 17 LOW-VOLTAGE DETECTOR
(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H^Note.
Figure 17-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Address: FF51H, After reset: 00H^Note R/W
Symbol
7
6
5
LVIS
0
0
0
4
3
2
1
0
0
LVIS3
LVIS2
LVIS1
LVIS0
LVIS3
LVIS2
LVIS1
LVIS0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
Other than above
Note Retained only after a reset by LVI.
Detection level
VLVI0 (4.3 V ±0.2 V)
VLVI1 (4.1 V ±0.2 V)
VLVI2 (3.9 V ±0.2 V)
VLVI3 (3.7 V ±0.2 V)
VLVI4 (3.5 V ±0.2 V)
VLVI5 (3.3 V ±0.15 V)
VLVI6 (3.1 V ±0.15 V)
VLVI7 (2.85 V ±0.15 V)
VLVI8 (2.6 V ±0.1 V)
VLVI9 (2.35 V ±0.1 V)
Setting prohibited
Cautions 1. Bits 4 to 7 must be set to 0.
2. If values other than same values are written during LVI operation, the value
becomes undefined at the very moment it is written, and thus be sure to stop LVI
(bit 7 of LVIM register (LVION) = 0) before writing.
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User’s Manual U17446EJ5V0UD