UPD78F9234MC-5A4-A Datasheet, PDF (89/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATORS
Figure 5-14. Status Transition of Low-Speed Internal Oscillation
Power
application
VDD > 2.1 V (TYP.)
Reset by
power-on-clear
Reset signal
Select by option byte
if low-speed internal oscillator
can be stopped or not
Can be stopped
Clock source of
WDT is selected
by software^Note
Low-speed internal
oscillator can be stopped
LSRSTOP = 1
LSRSTOP = 0
Low-speed internal
oscillator stops
Cannot be stopped
Low-speed internal
oscillator cannot be stopped
Clock source of
WDT is fixed to fRL
Note The clock source of the watchdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details,
refer to CHAPTER 9 WATCHDOG TIMER.
User’s Manual U17446EJ5V0UD
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