UPD78F9234MC-5A4-A Datasheet, PDF (288/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 FLASH MEMORY
(1) Flash programming mode control register (FLPMC)
This register is used to set the operation mode when data is written to the flash memory in the self
programming mode, and to read the set value of the protect byte.
Data can be written to FLPMC only in a specific sequence (refer to 19.8.3 (2) Flash protect command
register (PFCMD)) so that the application system does not stop by accident because of malfunctions due to
noise or program hang-ups.
This register is set with an 8-bit memory manipulation instruction.
Reset signal generation makes the contents of this register undefined.
Figure 19-10. Format of Flash Programming Mode Control Register (FLPMC)
Address: FFA2H
After reset: Undefined^{Note 1}
R/W^{Note 2}
Symbol
7
6
5
4
3
2
1
FLPMC
0
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0
0
0
FLSPM
FLSPM
0
1
Selection of operation mode during self programming mode
Normal mode
This is the normal operation status. Executing the HALT instruction sets
standby status.
Self programming mode
Self programming commands can be executed by executing the specific
sequence to change modes while in normal mode.
Set a command, an address, and data to be written, then execute the HALT
instruction to execute self programming.
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 ^{The set value of the protect byte}
is read to these bits.
Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect
byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released.
2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only.
Cautions 1. Cautions in the case of setting the self programming mode, refer to 19.8.2
Cautions on self programming function.
2. Set the CPU clock beforehand so that it is 1 MHz or higher during self
programming.
3. Execute self programming after executing the NOP and HALT instructions
immediately after executing a specific sequence to set self programming
mode. At this time, the HALT instruction is automatically released after 10
μs (MAX.) + 2 CPU clocks (fCPU).
4. If the clock of the oscillator or an external clock is selected as the system
clock, execute the NOP and HALT instructions immediately after executing a
specific sequence to set self programming mode, wait for 8 μs after
releasing the HALT status, and then execute self programming.
5. Clear the value of the FLCMD register to 00H immediately before setting to
self programming mode and normal mode.
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User’s Manual U17446EJ5V0UD