UPD78F9234MC-5A4-A Datasheet, PDF (253/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 15 RESET FUNCTION
Figure 15-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed internal oscillation clock or external clock input
High-speed internal oscillation clock or
external clock input
CPU clock
Watchdog overflow
Normal operation
in progress
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Operation stops because option
byte is referenced^{Note 1}.
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Hi-Z
Note 2
Notes 1. The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
2. Set high level output using software.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
<2> With crystal/ceramic oscillation clock
Crystal/ceramic
oscillation clock
CPU clock
Watchdog overflow
Normal operation
in progress
Reset period
(oscillation stops)
Oscillation stabilization
time (2¹⁰/fX to 2¹⁷/fX)
Normal operation
(reset processing, CPU clock)
Operation stops because option
byte is referenced^{Note 1}.
Internal reset signal
Port pin
Hi-Z
(except P130)
Port pin
(P130)
Note 2
Notes 1. The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
2. Set high level output using software.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remarks 1. fX: System clock oscillation frequency
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
User’s Manual U17446EJ5V0UD
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