UPD78F9234MC-5A4-A Datasheet, PDF (156/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 9 WATCHDOG TIMER
9.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
Generation of reset signal sets this register to 67H.
Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF48H After reset: 67H R/W
Symbol
7
6
5
WDTM
0
1
1
4
WDCS4
3
WDCS3
2
WDCS2
1
WDCS1
0
WDCS0
WDCS4^{Note 1} WDCS3^{Note 1}
Operation clock selection
0
0
Low-speed internal oscillation clock (fRL)
0
1
System Clock (fX)
1
×
Watchdog timer operation stopped
WDCS2^{Note 2} WDCS1^{Note 2} WDCS0^{Note 2}
Overflow time setting
During low-speed internal
oscillation clock operation
During system clock operation
0
0
0
2¹¹/fRL (4.27 ms)
2¹³/fX (819.2 μs)
0
0
1
2¹²/fRL (8.53 ms)
2¹⁴/fX (1.64 ms)
0
1
0
2¹³/fRL (17.07 ms)
2¹⁵/fX (3.28 ms)
0
1
1
2¹⁴/fRL (34.13 ms)
2¹⁶/fX (6.55 ms)
1
0
0
2¹⁵/fRL (68.27 ms)
1
0
1
2¹⁶/fRL (136.53 ms)
1
1
0
2¹⁷/fRL (273.07 ms)
2¹⁷/fX (13.11 ms)
2¹⁸/fX (26.21 ms)
2¹⁹/fX (52.43 ms)
1
1
1
2¹⁸/fRL (546.13 ms)
2²⁰/fX (104.86 ms)
Notes 1.
2.
If “low-speed internal oscillator cannot be stopped” is specified by the option byte, this cannot
be set. The low-speed internal oscillation clock will be selected no matter what value is
written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
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User’s Manual U17446EJ5V0UD