UPD78F9234MC-5A4-A Datasheet, PDF (117/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-29. Control Register Settings for PPG Output Operation
(a) Capture/compare control register 00 (CRC00)
7
6
5
4
3 CRC002 CRC001 CRC000
CRC00 0
0
0
0
0
0
×
0
CR000 used as compare register
CR010 used as compare register
(b) 16-bit timer output control register 00 (TOC00)
7 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
TOC00 0
0
0
1 0/1 0/1 1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting "11" is prohibited).
Inverts output on match between TM00 and CR010.
Disables one-shot pulse output.
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000 3
PRM00 0/1 0/1 0/1 0/1 0
2 PRM001 PRM000
0 0/1 0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
(d) 16-bit timer mode control register 00 (TMC00)
7
6
5
4 TMC003 TMC002 TMC001 OVF00
TMC00 0
0
0
0
1
1
0
0
Clears and starts on match between TM00 and CR000.
Cautions 1. Values in the following range should be set in CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark ×: Don’t care
User’s Manual U17446EJ5V0UD
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