UPD78F9234MC-5A4-A Datasheet, PDF (36/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (the stack area cannot be set except internal high-speed RAM area).
Figure 3-7. Stack Pointer Configuration
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SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.
Cautions 1.
2.
Since generation of reset signal makes the SP contents undefined, be sure to initialize
the SP before using the stack memory.
Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits
can be actually set.
Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the high-
speed RAM area, since 0FF00H is in the SFR area and not in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to
become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted
to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer.
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User’s Manual U17446EJ5V0UD