UPD78F9234MC-5A4-A Datasheet, PDF (267/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 17 LOW-VOLTAGE DETECTOR
(2) When used as interrupt
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
register (LVIS).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.
<6> Clear the interrupt request flag of LVI (LVIIF) to 0.
<7> Release the interrupt mask flag of LVI (LVIMK).
<8> Execute the EI instruction (when vector interrupts are used).
Figure 17-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to
<7> in this figure correspond to <1> to <7> above.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Figure 17-5. Timing of Low-Voltage Detector Interrupt Signal Generation
Supply voltage (VDD)
LVI detection voltage
(VLVI)
POC detection voltage
(VPOC)
<2>
LVIMK flag
(set by software)
<1>
Note 1
<7> Cleared by software
LVION flag
(set by software)
<3>
<4> 0.2 ms or longer
LVIF flag
INTLVI
<5>
Note 2
Time
LVIIF flag
Internal reset signal
Note 2
<6>
Note 2 Cleared by software
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. An interrupt request signal (INTLVI) may be generated, and the LVIF and LVIIF flags may be set to 1.
Remark <1> to <7> in Figure 17-5 above correspond to <1> to <7> in the description of “when starting operation”
in 17.4 (2) When used as interrupt.
User’s Manual U17446EJ5V0UD
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