UPD78F9234MC-5A4-A Datasheet, PDF (257/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 15 RESET FUNCTION
15.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0S/KB1+. The reset control flag register (RESF) is used to
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
Reset signal generation by RESET input or power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Figure 15-5. Format of Reset Control Flag Register (RESF)
Address: FF54H After reset: 00H^Note R
Symbol
7
6
5
4
3
2
1
RESF
0
0
0
WDTRF
0
0
0
0
LVIRF
WDTRF
0
1
Internal reset request by watchdog timer (WDT)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
LVIRF
Internal reset request by low-voltage detector (LVI)
0
Internal reset request is not generated, or RESF is cleared.
1
Internal reset request is generated.
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 15-2.
Table 15-2. RESF Status When Reset Request Is Generated
Reset Source RESET Input
Flag
WDTRF
Cleared (0)
LVIRF
Reset by POC Reset by WDT Reset by LVI
Cleared (0)
Set (1)
Held
Held
Set (1)
User’s Manual U17446EJ5V0UD
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