UPD78F9234MC-5A4-A Datasheet, PDF (163/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 9 WATCHDOG TIMER
(2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP
instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, operation stops for 34 μs (TYP.) and then counting is started again using the operation clock before the
operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
Figure 9-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal Oscillation Clock)
Normal
CPU operation operation
fCPU
fRL
Watchdog timer
Operating
<1> CPU clock: Crystal/ceramic oscillation clock
STOP
Operation
stopped^Note
Oscillation stabilization time
Oscillation stopped
Oscillation stabilization time
(set by OSTS register)
Operation stopped
Operating
Normal operation
<2> CPU clock: High-speed internal oscillation clock or external clock input
Normal
CPU operation ^operation
STOP
Operation
stopped^Note
Normal operation
fCPU
Oscillation stopped
fRL
Watchdog timer
Operating
Operation stopped
Operating
Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).
User’s Manual U17446EJ5V0UD
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