UPD78F9234MC-5A4-A Datasheet, PDF (153/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 15 RESET FUNCTION.
Table 9-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
During Low-Speed Internal Oscillation Clock
Operation
During System Clock Operation
2¹¹/fRL (4.27 ms)
2¹²/fRL (8.53 ms)
2¹³/fRL (17.07 ms)
2¹⁴/fRL (34.13 ms)
2¹⁵/fRL (68.27 ms)
2¹³/fX (819.2 μs)
2¹⁴/fX (1.64 ms)
2¹⁵/fX (3.28 ms)
2¹⁶/fX (6.55 ms)
2¹⁷/fX (13.11 ms)
2¹⁶/fRL (136.53 ms)
2¹⁸/fX (26.21 ms)
2¹⁷/fRL (273.07 ms)
2¹⁹/fX (52.43 ms)
2¹⁸/fRL (546.13 ms)
2²⁰/fX (104.86 ms)
Remarks 1. fRL: Low-speed internal oscillation clock frequency
2. fX: System clock oscillation frequency
3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.
The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip
low-speed internal oscillator as shown in Table 9-2.
User’s Manual U17446EJ5V0UD
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