UPD78F9234MC-5A4-A Datasheet, PDF (317/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 FLASH MEMORY
(2) Write to internal verify
<1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)
<2> Specification of source data for write
<3> Execution of byte write → Error check (<1> to <10> in 19.8.8)
<4> <3> is repeated until all data are written.
<5> Execution of internal verify 2 → Error check (<1> to <11> in 19.8.9)
<6> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)
Figure 19-26. Example of Operation When Command Execution Time Should Be Minimized
(from Write to Internal Verify)
Write to internal verify
Figure 19-18
<1> to <7>
<1> Shift to self programming
mode
<2> Set source data for write
Figure 19-22
<1> to <10>
Figure 19-23
<1> to <11>
Figure 19-19
<1> to <6>
<3> Execute byte write command
<3> Check execution result
(VCERR and WEPRERR flags)
Normal
Abnormal
Yes
<4> All data written?
No
<5> Execute internal verify 2
command
<5> Check execution result
(VCERR and WEPRERR flags)
Abnormal
Normal
<6> Shift to normal mode
Normal termination
Abnormal termination^Note
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <6> in Figure 19-26 correspond to <1> to <6> in 19.8.10 (2) above.
User’s Manual U17446EJ5V0UD
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