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UPD78F9234MC-5A4-A Datasheet, PDF (339/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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CHAPTER 21 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
Bytes Clocks
Operation
MOVW
XCHW
ADD
ADDC
SUB
rp, #word
AX, saddrp
saddrp, AX
AX, rp
rp, AX
AX, rp
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
3
2
2
Note
1
Note
1
Note
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6 rp â word
6 AX â (saddrp)
8 (saddrp) â AX
4 AX â rp
4 rp â AX
8 AX â rp
4 A, CY â A + byte
6 (saddr), CY â (saddr) + byte
4 A, CY â A + r
4 A, CY â A + (saddr)
8 A, CY â A + (addr16)
6 A, CY â A + (HL)
6 A, CY â A + (HL + byte)
4 A, CY â A + byte + CY
6 (saddr), CY â (saddr) + byte + CY
4 A, CY â A + r + CY
4 A, CY â A + (saddr) + CY
8 A, CY â A + (addr16) + CY
6 A, CY â A + (HL) + CY
6 A, CY â A + (HL + byte) + CY
4 A, CY â A â byte
6 (saddr), CY â (saddr) â byte
4 A, CY â A â r
4 A, CY â A â (saddr)
8 A, CY â A â (addr16)
6 A, CY â A â (HL)
6 A, CY â A â (HL + byte)
Flag
Z AC CY
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Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
Userâs Manual U17446EJ5V0UD
337
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