UPD78F9234MC-5A4-A Datasheet, PDF (342/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 21 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
CALL
CALLT
!addr16
[addr5]
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
Bytes Clocks
Operation
3
6
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
1
8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
1
6
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
1
8
PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2),
SP ← SP + 3
1
2 (SP − 1) ← PSW, SP ← SP − 1
1
4
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
1
4 PSW ← (SP), SP ← SP + 1
1
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
2
8 SP ← AX
2
6 AX ← SP
3
6 PC ← addr16
2
6 PC ← PC + 2 + jdisp8
1
6
PCH ← A, PCL ← X
2
6 PC ← PC + 2 + jdisp8 if CY = 1
2
6 PC ← PC + 2 + jdisp8 if CY = 0
2
6 PC ← PC + 2 + jdisp8 if Z = 1
2
6 PC ← PC + 2 + jdisp8 if Z = 0
4
10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
4
10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
3
8 PC ← PC + 3 + jdisp8 if A.bit = 1
4
10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
4
10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
4
10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
3
8 PC ← PC + 3 + jdisp8 if A.bit = 0
4
10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
2
6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
2
6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
3
8 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
1
2 No Operation
3
6 IE ← 1 (Enable Interrupt)
3
6 IE ← 0 (Disable Interrupt)
1
2 Set HALT Mode
1
2 Set STOP Mode
Flag
Z AC CY
RRR
RRR
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
340
User’s Manual U17446EJ5V0UD