UPD78F9234MC-5A4-A Datasheet, PDF (225/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 12 MULTIPLIER
12.4 Multiplier Operation
The multiplier of the 78K0S/KB1+ can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 12-3 shows the
operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.
<1> Counting is started by setting the MULST0, and then multiplication of MRA0 and MRB0 begins. The
multiplication result is held after 16 clocks, using the CPU clock.
<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value is
incremented by one.
<3> When the 3-bit counter value is 111B, MULST0 is cleared and the operation is stopped. At this time, MUL0
holds the operation result.
Remark When MULST0 is low, the 3-bit counter is cleared.
CPU clock
Figure 12-3. Multiplier Operation Timing (Example of AAH × D3H)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MRA0
MRB0
MULST0
3-bit counter
MUL0
AA
D3
<1>
000B
<2>
<3>
001B 010B 011B 100B 101B 110B 111B
000B
Operation in progress^Note
8C1E
Note Mid-calculation results are read by referencing MUL0 while calculating.
The source code of this example is shown in the following page.
User’s Manual U17446EJ5V0UD
223