UPD78F9234MC-5A4-A Datasheet, PDF (111/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
7
CRC00 0
(a) Capture/compare control register 00 (CRC00)
6
5
4
3 CRC002 CRC001 CRC000
0
0
0
0
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000^Note.
CR010 used as capture register
(b) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000 3
PRM00 0/1 0/1 0
1
0
2 PRM001 PRM000
0 0/1 0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
7
TMC00 0
(c) 16-bit timer mode control register 00 (TMC00)
6
5
4 TMC003 TMC002 TMC001 OVF00
0
0
0
0
1 0/1 0
Free-running mode
Note If the valid edge of the TI000 pin is specified to be both the rising and falling edges, 16-bit timer
capture/compare register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is
1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is
detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is
generated at that timing.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
User’s Manual U17446EJ5V0UD
109