UPD78F9234MC-5A4-A Datasheet, PDF (85/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATORS
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator
(a)
VDD
RESET _H
Internal reset
System clock
CPU clock
(b)
(c)
Crystal/ceramic
oscillator clock
PCC = 02H, PPCC = 02H
Option byte is read.
System clock is selected.
(Operation stops^{Note 1})
Clock oscillation
stabilization
time^{Note 2}
Notes 1.
2.
Operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
The clock oscillation stabilization time for default start is selected by the option byte. For details, refer
to CHAPTER 18 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode
is released is selected by the oscillation stabilization time select register (OSTS).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) After the high-speed internal oscillation clock is generated, the option byte is referenced and the system
clock is selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 18
OPTION BYTE.
User’s Manual U17446EJ5V0UD
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