UPD78F9234MC-5A4-A Datasheet, PDF (87/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATORS
Figure 5-12. Timing of Default Start by External Clock Input
(a)
VDD
RESET _H
Internal reset
(b)
System clock
CPU clock
External clock input
PCC = 02H, PPCC = 02H
Option byte is read.
System clock is selected.
(Operation stops^Note)
Note Operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
Figure 5-13. Status Transition of Default Start by External Clock Input
Power
application
VDD > 2.1 V (TYP.)
Reset by
power-on-clear
Reset signal
External clock input
selected by option byte
Interrupt
HALT
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
HALT
instruction _STOP
instruction
Interrupt
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
User’s Manual U17446EJ5V0UD
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