UPD78F9234MC-5A4-A Datasheet, PDF (401/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

APPENDIX D LIST OF CAUTIONS
Function
Details of
Function
Cautions
(10/20)
Page
A/D
converter
Serial
interface
UART6
Input impedance
of ANI0 to ANI3
pins
In this A/D converter, the internal sampling capacitor is charged and sampling
is performed during sampling time.
Since only the leakage current flows other than during sampling and the
current for charging the capacitor also flows during sampling, the input
impedance fluctuates both during sampling and otherwise.
If the shortest conversion time of the reference voltage is used, to perform
sufficient sampling, it is recommended to make the output impedance of the
analog input source 1 kΩ or lower, or attach a capacitor of around 0.01 μ F to
0.1 μ F to the ANI0 to ANI3 pins (see Figure 10-19).
p.180
ADIF: Interrupt
request flag
The interrupt request flag (ADIF) is not cleared even if the analog input
channel specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just
before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact
A/D conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the
A/D conversion operation is resumed.
p.180
Conversion
results just after
A/D conversion
start
The first A/D conversion value immediately after A/D conversion starts may
not fall within the rating range if the ADCS bit is set to 1 within 1 μs after the
ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0.
Take measures such as polling the A/D conversion end interrupt request
(INTAD) and removing the first conversion result.
p.181
A/D conversion
result register
(ADCR, ADCRH)
read operation
When a write operation is performed to the A/D converter mode register
(ADM) and analog input channel specification register (ADS), the contents of
ADCR and ADCRH may become undefined. Read the conversion result
following conversion completion before writing to ADM and ADS. Using a
timing other than the above may cause an incorrect conversion result to be
read.
p.181
Operating current
at conversion
waiting mode
The DC characteristic of the operating current during the STOP mode is not
satisfied due to the conversion waiting mode (only the comparator consumes
power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode
register (ADM) are set to 0 and 1 respectively.
p.181
UART mode
The TXD6 output inversion function inverts only the transmission side and not
the reception side. To use this function, the reception side must be ready for
reception of inverted data.
p.182
If clock supply to serial interface UART6 is not stopped (e.g., in the HALT
mode), normal operation continues. If clock supply to serial interface UART6
is stopped (e.g., in the STOP mode), each register stops operating, and holds
the value immediately before clock supply was stopped. The TxD6 pin also
holds the value immediately before clock supply was stopped and outputs it.
However, the operation is not guaranteed after clock supply is resumed.
Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
p.182
If data is continuously transmitted, the communication timing from the stop bit
to the next start bit is extended two operating clocks of the macro. However,
this does not affect the result of communication because the reception side
initializes the timing when it has detected a start bit. Do not use the
continuous transmission function if the interface used in LIN communication
operation.
p.182
User’s Manual U17446EJ5V0UD
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