UPD78F9234MC-5A4-A Datasheet, PDF (233/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 13 INTERRUPT FUNCTIONS
(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
Reset signal generation clears INTM0 to 00H.
Figure 13-4. Format of External Interrupt Mode Register 0 (INTM0)
Address: FFECH After reset: 00H R/W
Symbol 7
6
5
4
3
2
1
0
INTM0 ES21 ES20 ES11 ES10 ES01 ES00
0
0
ES21
0
0
1
1
ES20
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP2 valid edge selection
ES11
0
0
1
1
ES10
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP1 valid edge selection
ES01
0
0
1
1
ES00
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP0 valid edge selection
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will
enable interrupts.
User’s Manual U17446EJ5V0UD
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