UPD78F9234MC-5A4-A Datasheet, PDF (281/419 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 FLASH MEMORY
78K0S/KB1+
RESET
Figure 19-6. Signal Collision (RESET Pin)
Signal collision
Dedicated flash memory programmer
connection signal
Reset signal generator
Output pin
In the flash memory programming mode, the signal output by the reset signal
generator collides with the signal output by the dedicated flash memory
programmer. Therefore, isolate the signal of the reset signal generator.
19.6.3 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
The state of the pins in the self programming mode is the same as that in the HALT mode.
19.6.4 Power supply
Connect the VDD pin to VDD of the flash memory programmer, and the VSS pin to VSS of the flash memory
programmer.
Supply the same other power supplies (AVREF and AVSS) as those in the normal operation mode.
User’s Manual U17446EJ5V0UD
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