PIC18F87K22 Datasheet, PDF (99/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
F86h
F85h
F84h
F83h
F82h
F81h
F80h
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
F5Fh
F5Eh
F5Dh
Note
PORTG
—
—
RG5
RG4
RG3
RG2
RG1
RG0
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
EECON2
EEPROM Control Register 2 (not a physical register)
TMR5H
Timer5 Register High Byte
TMR5L
Timer5 Register Low Byte
T5CON
TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC
RD16
TMR5ON
T5GCON
TMR5GE T5GPOL
T5GTM
T5GSPM
T5GGO/
T5DONE
T5GVAL
T5GSS1
T5GSS0
CCPR4H
Capture/Compare/PWM Register 4 High Byte
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
CCP4CON
—
—
DC4B1
DC4B0
CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCPR5H
Capture/Compare/PWM Register 5 High Byte
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3 CCP5M2 CCP5M1 CCP5M0
CCPR6H
Capture/Compare/PWM Register 6 High Byte
CCPR6L
Capture/Compare/PWM Register 6 Low Byte
CCP6CON
—
—
DC6B1
DC6B0
CCP6M3 CCP6M2 CCP6M1 CCP6M0
CCPR7H
Capture/Compare/PWM Register 7 High Byte
CCPR7L
Capture/Compare/PWM Register 7 Low Byte
CCP7CON
—
—
DC7B1
DC7B0
CCP7M3 CCP7M2 CCP7M1 CCP7M0
TMR4
Timer4 Register
PR4
Timer4 Period Register
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
SSP2BUF
SSP2ADD
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I²C™ Slave Mode. MSSP1 Baud Rate Reload Register in I²C Master Mode.
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSP2CON2
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
OSCCON2
—
SOSCRUN
—
—
SOSCGO
—
MFIOFS MFIOSEL
EEADRH
EEPROM Address Register High Byte
EEADR
EEPROM Address Register Low Byte
EEDATA
EEPROM Data Register
PIE6
—
—
—
EEIE
—
CMP3IE
CMP2IE
CMP1IE
RTCCFG
RTCEN
—
RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0
RTCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
RTCVALH
RTCC Value High Register Window Based on RTCPTR<1:0>
1: The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22).
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
Value on
POR, BOR
--xx xxxx
xxxx xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx-0 x000
---- ----
xxxx xxxx
xxxx xxxx
0000 0000
0000 0x00
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
1111 1111
-111 1111
xxxx xxxx
0000 0000
0000 0000
0000 0000
0100 0000
0100 0-00
-0-- 0-x0
0000 0000
0000 0000
0000 0000
---0 -000
0000 0000
xxxx xxxx
xxxx xxxx
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 99