PIC18F87K22 Datasheet, PDF (121/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
8.2 Address and Data Width
The PIC18F87K22 family of devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The ABW<1:0> bits determine both the program mem-
ory operating mode and the address bus width. The
available options are 20-bit, 16-bit and 12-bit, as well
as Microcontroller mode (external bus disabled).
Selecting a 16-bit or 12-bit width makes a correspond-
ing number of high-order lines available for I/O
functions. These pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a
16-Bit Addressing mode (ABW<1:0> = 01) disables
A<19:16> and allows PORTH<3:0> to function without
interruptions from the bus. Using the smaller address
widths allows users to tailor the memory bus to the size
of the external memory space for a particular design
while freeing up pins for dedicated I/O operation.
Because the ABW bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 8-2.
8.2.1
ADDRESS SHIFTING ON THE
EXTERNAL BUS
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the micro-
controller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
8.2.2 21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
This addressing mode is available in both 8-bit and
certain 16-Bit Data Width modes. Additional details are
provided in Section 8.6.3 “16-Bit Byte Select Mode”
and Section 8.7 “8-Bit Data Width Mode”.
TABLE 8-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Data Width
Address Width
Multiplexed Data and
Address Lines (and
Corresponding Ports)
Address Only Lines
(and Corresponding
Ports)
Ports Available
for I/O
8-bit
16-bit
12-bit
16-bit
20-bit
16-bit
20-bit
AD<7:0>
(PORTD<7:0>)
AD<15:0>
(PORTD<7:0>,
PORTE<7:0>)
AD<11:8>
(PORTE<3:0>)
AD<15:8>
(PORTE<7:0>)
A<19:16>, AD<15:8>
(PORTH<3:0>,
PORTE<7:0>)
—
A<19:16>
(PORTH<3:0>)
PORTE<7:4>,
All of PORTH
All of PORTH
—
All of PORTH
—
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 121