PIC18F87K22 Datasheet, PDF(363/548 Page) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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PIC18F87K22 Datasheet, PDF (363/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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PIC18F87K22 FAMILY

TABLE 23-2: REGISTERS ASSOCIATED WITH A/D MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

PIE1

IPR1

PIR3

PIE3

IPR3

ADRESH

ADRESL

GIE/GIEH PEIE/GIEL TMR0IE

PSPIF

ADIF

RC1IF

PSPIE

ADIE

RC1IE

PSPIP

ADIP

RC1IP

TMR5GIF

â

RC2IF

TMR5GIE

â

RC2IE

TMR5GIP

â

RC2IP

A/D Result Register High Byte

A/D Result Register Low Byte

INT0IE

TX1IF

TX1IE

TX1IP

TX2IF

TX2IE

TX2IP

RBIE

SSP1IF

SSP1IE

SSP1IP

CTMUIF

CTMUIE

CTMUIP

TMR0IF

TMR1GIF

TMR1GIE

TMR1GIP

CCP2IF

CCP2IE

CCP2IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

CCP1IF

CCP1IE

CCP1IP

RBIF

TMR1IF

TMR1IE

TMR1IP

RTCCIF

RTCCIE

RTCCIP

ADCON0

â

CHS4

CHS3

CHS2

CHS1

CHS0 GO/DONE ADON

ADCON1

TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0

ADCON2

ADFM

â

ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

ANCON0

ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0

ANCON1

ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8

ANCON2

ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16

CCP2CON

PORTA

TRISA

P2M1

RA7(2)

TRISA7(2)

P2M0

RA6(2)

TRISA6(2)

DC2B1

RA5

TRISA5

DC2B0

RA4

TRISA4

CCP2M3

RA3

TRISA3

CCP2M2

RA2

TRISA2

CCP2M1

RA1

TRISA1

CCP2M0

RA0

TRISA0

PORTF

RF7

RF6

RF5

RF4

RF3

RF2

RF1

â

TRISF

PORTG

TRISF7

TRISF6

â

TRISF5

RG5(3)

TRISF4

RG4

TRISF3

RG3

TRISF2

RG2

TRISF1

RG1

â

RG0

TRISG

PORTH(1)

TRISH(1)

â

RH7

TRISH7

â

RH6

TRISH6

â

RH5

TRISH5

TRISG4

RH4

TRISH4

TRISG3

RH3

TRISH3

TRISG2

RH2

TRISH2

TRISG1

RH1

TRISH1

TRISG0

RH0

TRISH0

PMD0

CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD

Legend: â = unimplemented, read as â0â. Shaded cells are not used for A/D conversion.

Note 1: This register is not implemented on 64-pin devices.

2: These bits are available only in certain oscillator modes, when the FOSC2 Configuration bit = 0. If that

Configuration bit is cleared, this signal is not implemented.

3: Bit available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, bit is unimplemented.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS39960B-page 363

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