PIC18F87K22 Datasheet, PDF (174/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
12.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISD and LATD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: These pins are configured as digital inputs
on any device Reset.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit, RDPU (PADCFG1<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD<7:0>). The TRISD bits are also
overridden.
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. For additional information, see
Section 12.11 “Parallel Slave Port”.
The PORTD also has the I²C and SPI functionality on
RD4, RD5 and RD6. The pins for SPI are also configu-
rable for open-drain output. Open-drain configuration is
selected by setting bit, SSP2OD (ODCON1<0>).
RD0 has a CTMU functionality. RD1 has the functional-
ity for the Timer5 clock input and Timer7 external clock
gate input.
EXAMPLE 12-4: INITIALIZING PORTD
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
0CFh
TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
TABLE 12-7: PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/PSP0/
AD0/CTPLS
RD0
PSP0⁽¹⁾
AD0⁽²⁾
0
O
DIG LATD<0> data output.
1
I
ST PORTD<0> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 0.
CTPLS
x
O
DIG CTMU pulse generator output.
RD1/PSP1/
AD1/T5CKI/
T7G
RD1
PSP1⁽¹⁾
AD1⁽²⁾
0
O
DIG LATD<1> data output.
1
I
ST PORTD<1> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 1.
T5CKI
x
I
ST Timer5 clock input.
T7G
x
I
ST Timer7 external clock gate input.
RD2/PSP2/AD2
RD2
0
O
DIG LATD<2> data output.
PSP2⁽¹⁾
AD2⁽²⁾
1
I
ST PORTD<2> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 2.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
I²C = I²C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PSP is available only in Microcontroller mode.
This feature is available only on PIC18F8XK22 devices.
DS39960B-page 174
Preliminary
 2010 Microchip Technology Inc.